Low Hardware Layered Decoding Architecture for LDPC Code
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Research Paper | Electronics & Telecommunication Engineering | India | Volume 2 Issue 3, March 2013

Low Hardware Layered Decoding Architecture for LDPC Code

N. Aravind, L. Praveen Kumar

Low density parity check (LDPC) codes have been extensively adopted in next-generation forward error correction applications because they achieve very good performance using the iterative decoding approach of the belief-propagation (BP). The basic decoder design for achieving the highest decoding throughput is to allocate processors corresponding to all check and variable nodes, together with an interconnection network. In this fully-parallel decoder architecture, the hardware complexity due to the routing overhead is very large. Therefore, much of the work on LDPC decoder design has been directed towards achieving optimal tradeoffs between hardware complexity and decoding throughput. In particular, a time-multiplexed or folded approach, which is known as partially parallel decoder architecture, has been proposed. Low hardware layered decoding architecture for LDPC code scheme is proposed using only one switch network with direct connections. This method requires only one shuffle network, rather than the two shuffle networks which are used in conventional designs. In addition, this project can be extended to block parallel decoding scheme by suitably mapping between required memory banks and processing units in order to increase the decoding throughput.

Keywords: Decoding, field-programmable gate array, FPGA, forward error correction, low density parity check, LDPC

Edition: Volume 2 Issue 3, March 2013

Pages: 1 - 4

Share this Article

How to Cite this Article?

N. Aravind, L. Praveen Kumar, "Low Hardware Layered Decoding Architecture for LDPC Code", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSRON2013490, Volume 2 Issue 3, March 2013, 1 - 4

58 PDF Views | 52 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'FPGA'

Research Paper, Electronics & Telecommunication Engineering, India, Volume 2 Issue 3, March 2013

Pages: 1 - 4

Low Hardware Layered Decoding Architecture for LDPC Code

N. Aravind, L. Praveen Kumar

Share this Article

Research Paper, Electronics & Telecommunication Engineering, India, Volume 2 Issue 2, February 2013

Pages: 614 - 622

FPGA Implementation of Codec Design for Optimal Code Rate Crosstalk Avoidance Codes

K. Ramesh, E. Srinivas

Share this Article
Top