Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Downloads: 128 | Weekly Hits: ⮙1 | Monthly Hits: ⮙8

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 7, July 2013

Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques

Madhavi Anupoju, M. Sunil Prakash

In present days, there is a need for ever increasing high performance and low power devices, these devices need to meet performance constraints like speed, area& power. This paper describes the area and speed constraints of a 16 bit processor with the implementation of three state encoding techniques binary, one- hot & gray coding technique. The processor architecture is designed using Verilog HDL, simulated on Modelsim and synthesized on Precision RTL synthesis tool & on XILINX ISE 12.1 for the Spartan3E FPGA. From the synthesis reports it is observed that One-hot encoding would perform with speed 28 % and Gray code would perform with speed 14 % more than binary encoding technique, but both of them require more area compared to binary encoding technique.

Keywords: FPGA, Precision synthesis, State encoding techniques, VLSI circuits, VERILOG hardware description language

Edition: Volume 2 Issue 7, July 2013

Pages: 88 - 92

Share this Article

How to Cite this Article?

Madhavi Anupoju, M. Sunil Prakash, "Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSRON20131114, Volume 2 Issue 7, July 2013, 88 - 92

Enter Your Registered Email Address





Similar Articles with Keyword 'FPGA'

Downloads: 133 | Weekly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016

Pages: 422 - 426

An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor

R. Kiruthikaa, S. Salaiselvapathy

Share this Article

Downloads: 53 | Weekly Hits: ⮙4 | Monthly Hits: ⮙25

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 3, March 2021

Pages: 143 - 150

VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem

Ragi R G, Jayaraj U Kidav, Roshith K

Share this Article

Downloads: 98 | Weekly Hits: ⮙2 | Monthly Hits: ⮙8

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3033 - 3036

FIR Interpolation Filter for Multi-Standard Digital Up Converter Using FPGA

Chaithra M. R., Yashwanth N

Share this Article

Downloads: 99 | Weekly Hits: ⮙1 | Monthly Hits: ⮙11

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

Efficient Implementation of Digital Receiver on FPGA

M. Sravani, B. Madhavi

Share this Article

Downloads: 101 | Weekly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2468 - 2472

VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture

Ghanshyam A. Chune, Vijay Bagdi

Share this Article

Similar Articles with Keyword 'VLSI circuits'

Downloads: 110 | Weekly Hits: ⮙1 | Monthly Hits: ⮙10

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 1297 - 1300

A Wide Range Level Shifter Using a Self Biased Cascode Current Mirror

Tejas S. Joshi, Priya M. Nerkar

Share this Article

Downloads: 114 | Weekly Hits: ⮙1 | Monthly Hits: ⮙14

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2374 - 2378

Circuit under Test Verification with MSIC Test Pattern Generator

Parvathy Chandra, Vishnu V. S.

Share this Article

Downloads: 121 | Weekly Hits: ⮙2 | Monthly Hits: ⮙15

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 159 - 164

Analysis of Low Power Test Pattern Generator by Using Low Power Linear Feedback Shift Register (LP-LFSR)

Nelli Shireesha, Katakam Divya

Share this Article

Downloads: 121 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 1226 - 1230

VLSI Implementation for BIST Controller using Signed and Unsigned Multiplier

Dileep Kumar, Ghanshyam

Share this Article

Downloads: 123 | Weekly Hits: ⮙1 | Monthly Hits: ⮙15

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 1585 - 1589

Adiabatic Logic Circuits for Low Power VLSI Applications

Durgesh Patel, Dr. S. R. P. Sinha, Meenakshi Shree

Share this Article

Similar Articles with Keyword 'VERILOG hardware description language'

Downloads: 128 | Weekly Hits: ⮙1 | Monthly Hits: ⮙8

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 88 - 92

Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques

Madhavi Anupoju, M. Sunil Prakash

Share this Article

Downloads: 137 | Weekly Hits: ⮙5 | Monthly Hits: ⮙12

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 7, July 2016

Pages: 311 - 314

Fusion of March Algorithms in Counter based BIST for the Detection of Faults in RAM

Twinkle Koshy, Manjusree S

Share this Article



Top