Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 7, July 2013

Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques

Madhavi Anupoju, M. Sunil Prakash

In present days, there is a need for ever increasing high performance and low power devices, these devices need to meet performance constraints like speed, area& power. This paper describes the area and speed constraints of a 16 bit processor with the implementation of three state encoding techniques binary, one- hot & gray coding technique. The processor architecture is designed using Verilog HDL, simulated on Modelsim and synthesized on Precision RTL synthesis tool & on XILINX ISE 12.1 for the Spartan3E FPGA. From the synthesis reports it is observed that One-hot encoding would perform with speed 28 % and Gray code would perform with speed 14 % more than binary encoding technique, but both of them require more area compared to binary encoding technique.

Keywords: FPGA, Precision synthesis, State encoding techniques, VLSI circuits, VERILOG hardware description language

Edition: Volume 2 Issue 7, July 2013

Pages: 88 - 92

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How to Cite this Article?

Madhavi Anupoju, M. Sunil Prakash, "Performance Evolution of 16 Bit Processor in FPGA using State Encoding Techniques ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSRON20131114, Volume 2 Issue 7, July 2013, 88 - 92

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