International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064

Downloads: 111

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 5, May 2013

High Performance Pipelined Design for FFT Processor Based on FPGA

A.A. Raut | S. M. Kate

Abstract: It is important to develop a high-performance FFT processor to meet the requirements of real time and low cost in many different systems. So a radix-2 pipelined FFT processor based on Field Programmable Gate Array (FPGA) for Wireless Local Area Networks (WLAN) is proposed. Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. This paper concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation-In-Time (DIT) domain, Radix-2 algorithm, this paper uses VHDL as a design entity, and their Synthesis by Xilinx Synthesis Tool on SPARTAN kit has been done. The input of Fast Fourier transform has been given by a PS2 KEYBOARD using a test bench and output has been displayed using the waveforms on the Xilinx Design Suite 12.1. The synthesis results show that the computation for calculating the 32-point Fast Fourier transform is efficient in terms of speed. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors, and also can achieve cost effectively ASIC-like performance with lower development time, and risks. This results show that the processor achieves higher throughput and lower area and latency

Keywords: FFT, radix-2, FPGA, Butterfly, VHDL

Edition: Volume 2 Issue 5, May 2013,

Pages: 107 - 111

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How to Cite this Article?

A.A. Raut, S. M. Kate, "High Performance Pipelined Design for FFT Processor Based on FPGA", International Journal of Science and Research (IJSR), Volume 2 Issue 5, May 2013, pp. 107-111,

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