Implementation of Space Time Block Codes for Wimax Applications
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064


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Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 3, March 2013

Implementation of Space Time Block Codes for Wimax Applications

M Ravi, A Madhusudhan

This paper describes the concept, architecture, development and demonstration of a real time, maximum likelihood Alamouti decoder for a wireless 4-transmit 4-receiver multiple input and multiple output (MIMO) Smart Antenna Software Radio Test System (SASRATS) platform. It is implemented on a Xilinx Vertex 2 Pro Field Programmable Gate Array (FPGA). Hardware, firmware, use of the Xilinx Core Generator Intellectual Property modules and experimental verification of the decoder are discussed.

Keywords: real-time implementation, Alamouti, FPGA, maximum likelihood decoder, MIMO

Edition: Volume 2 Issue 3, March 2013

Pages: 52 - 56

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How to Cite this Article?

M Ravi, A Madhusudhan, "Implementation of Space Time Block Codes for Wimax Applications", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSROFF2013077, Volume 2 Issue 3, March 2013, 52 - 56

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