Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 3, March 2013
EEPROM Memory Controller Architecture for an Out of Order Execution
Shankaran S, K. Hari Priya
Abstract: In modern day computer technology the time taken to access the information from the memory is larger compared to the time taken to execute the instructions. So we have to reduce the access time of the processor. An attempt has been made to reduce the time taken to execute the instructions by implementing several executing techniques so that the processor does not remain idle. In sequential execution the processor has to remain idle for a longer time in this process the processor is not used efficiently. Therefore to overcome this barrier out of order execution has been proposed by which the time taken to execute the instructions is reduced to a greater extent. In out of order execution the response time is reduced. The out of order also allows a prioritized handling of multiple operations. EEPROM is a nonvolatile memory which can be programmed and erased by using field electron emission the main characteristic of EEPROM is the way the memory programs and erases. Electrically erasable programmable read only memory controller architecture has been employed to enhance the performance of the system by executing the instructions in decoupled and out of order pattern so that the execution of instruction takes place at a faster rate and the efficiency of the processor is increased.
Keywords: EEPROM, RAM, DRAM, SRAM, OoO
Edition: Volume 2 Issue 3, March 2013,
Pages: 5 - 8
How to Cite this Article?
Shankaran S, K. Hari Priya, "EEPROM Memory Controller Architecture for an Out of Order Execution", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=IJSROFF2013071, Volume 2 Issue 3, March 2013, 5 - 8
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