Research Paper | Electronics & Telecommunication Engineering | India | Volume 2 Issue 1, January 2013
Design and Implementation of DDR SDRAM Controller using Verilog
Priyanka Bibay, Anil Kumar Sahu, Vivek Kumar Chandra
Double Data Rate Synchronous DRAM (DDR SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. The DDR SDRAM is an enhancement to the conventional SDRAM running at bus speed over 75MHz. The DDR SDRAM (referred to as DDR) doubles the bandwidth of the memory by transferring data twice per cycle on both the rising and falling edges of the clock signal. The designed DDR Controller supports data width of 64 bits, Burst Length of 4 and CAS (Column Address Strobe) latency of 2. DDR Controller provides a synchronous command interface to the DDR SDRAM Memory along with several control signals. In this paper, the implementation has been done in Verilog HDL by using Xilinx ISE 9.2i and Modelsim 6.4b.
Keywords: Double Data Rate, Column Address Strobe CAS, Synchronous Dynamic RAM
Edition: Volume 2 Issue 1, January 2013
Pages: 320 - 324
How to Cite this Article?
Priyanka Bibay, Anil Kumar Sahu, Vivek Kumar Chandra, "Design and Implementation of DDR SDRAM Controller using Verilog", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSROFF130201036, Volume 2 Issue 1, January 2013, 320 - 324
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