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Research Paper | Electronics & Communication Engineering | India | Volume 9 Issue 2, February 2020
Reduction of Leakage Current in CMOS Circuits
Dr S Rooban, Ch Silas, N Venkaiah, Shaik Karishma
Abstract: The leakage control dispersal has gotten one of most testing issue and going up against issue in low power vlsi circuit plan especially with on-chip contraptions as it copies for ordinary interims. The cutting back of point of confinement voltage had accepted the noteworthy activity towards increase in subthreshold leakage current there by making the static (leakage) control dissemination exceptionally high and all out power scattering may fundamentally be contributed by leakage control dispersal. The current work is identified with which we can stop the leakage of current up to a degree by utilizing tired attendant system. Sleepy Keeper utilizes sleep transistors and two extra transistors to lessen the power during sleep mode the control when the battery activity gadgets with length time fluctuation as indicated by backup mode might be depleted out quickly the to the leakage control. . A complete report is investigation of different leakage control limiting procedures have been introduced in this paper. The present zone of study and its relating investigation are essentially centered around circuit capacity of execution parameters of tired Keeper. Anyway, for applications invests most span of energy in sleep or backup mode with superior Sleepy Keeper will give another period to vlsi configuration in the case of leakage control decrease.
Keywords: sleepy keeper, power dissipation, threshold voltage
Edition: Volume 9 Issue 2, February 2020,
Pages: 218 - 221
How to Cite this Article?
Dr S Rooban, Ch Silas, N Venkaiah, Shaik Karishma, "Reduction of Leakage Current in CMOS Circuits", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=ART20204552, Volume 9 Issue 2, February 2020, 218 - 221
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