Low Power and Area Efficient Carry Select Adder Using D-Flip Flop
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 8 Issue 11, November 2019

Low Power and Area Efficient Carry Select Adder Using D-Flip Flop

S. Muminthaj, S. Kayalvizhi, K. Sangeetha

Area, Power Consumption and Delay are the constituent factors in VLSI design that limits the performance of any circuit. This work presents a simple approach to reduce the area, power consumption and delay of CSLA architecture. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Carry Select Adder is efficient for low power application, produces the partial sum and carry by independently generating multiple carries. The proposed design has reduced area, low power consumption when compared to other adders in VLSI. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Keywords: CSLA Adder, RCA, BEC-1, D-FF, Multiplexer

Edition: Volume 8 Issue 11, November 2019

Pages: 964 - 967

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How to Cite this Article?

S. Muminthaj, S. Kayalvizhi, K. Sangeetha, "Low Power and Area Efficient Carry Select Adder Using D-Flip Flop", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20202769, Volume 8 Issue 11, November 2019, 964 - 967

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