M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 7 Issue 12, December 2018
Analytical Analysis of Current Comparator Circuit Based on CMOS with 0.5µm & 0.35µm Technology
Abstract: This paper presents current comparator designed by using CMOS having less power dissipation & less propagation delay. Power consumption and delay in propagation is a big problem can be reduced by the proper architecture. All designs have been implemented using two different technologies that is 0.35 & #181;m technologies with 3V supply voltage. There are many versions of comparator has come to improve the outcome. There is a comparison have been made with three earlier circuit comparing power dissipation and propagation delay and it has been found that the overall performance is better than the existing circuits. The proposed design of current comparator by using CMOS technology is having more speed with less power consumption.
Keywords: Current Comparator, CMOS, Propagation, Delay, low power consumption, slew rate
Edition: Volume 7 Issue 12, December 2018,
Pages: 427 - 430
How to Cite this Article?
Sweta Kumari Barnwal, "Analytical Analysis of Current Comparator Circuit Based on CMOS with 0.5µm & 0.35µm Technology", International Journal of Science and Research (IJSR), Volume 7 Issue 12, December 2018, pp. 427-430, https://www.ijsr.net/get_abstract.php?paper_id=ART20193437
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