Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Downloads: 131 | Weekly Hits: ⮙1 | Monthly Hits: ⮙11

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 7 Issue 5, May 2018

Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump

Pallavi. K. R, Dr. K. N. Muralidhara

The Phase Locked Loop (PLL) is a combined system of phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO), frequency divider (FD). The PLL is widely used in RF and wireless transceivers, optical fiber receivers and carrier synthesis in cellular telephones etc. The PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three stages- free running, capture and locked or tracking. Once the PLL is locked, it can track frequency changes in the incoming signals. In the proposed PLL, the designed PFD is free from dead zone. The single-event-transient hardened-by-design (SET-HBD) charge pump is used instead of traditional CP to overcome the single event effects (SEEs) such as single-event upset (SEU), multiple bit upset, single-event transient (SET), and latch up problems. Here we use the radiation hardened circuit and reference circuit along with the charge pump circuit. And the 5-stage current starved voltage controlled oscillator is used. And the divided by 4 frequency divider circuit is designed for feedback circuit using a 2-D flip-flops (N/4). The PLL design is implemented in cadence virtuoso 180nm technology with a supply voltage of 1.8V operates at a frequency of 1GHZ and all the simulations are done using cadence simulator.

Keywords: PLL, PFD, CPLPF, VCO, FD, SETHBD

Edition: Volume 7 Issue 5, May 2018

Pages: 727 - 732

Share this Article

How to Cite this Article?

Pallavi. K. R, Dr. K. N. Muralidhara, "Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20182573, Volume 7 Issue 5, May 2018, 727 - 732

Enter Your Registered Email Address





Similar Articles with Keyword 'PLL'

Downloads: 106 | Weekly Hits: ⮙3 | Monthly Hits: ⮙14

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 847 - 850

Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops

Nemitha B, Pradeep Kumar B. P

Share this Article

Downloads: 111 | Weekly Hits: ⮙3 | Monthly Hits: ⮙11

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 1144 - 1146

Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration

Dr. Manish Sharma, Asma Chishti

Share this Article

Downloads: 112 | Weekly Hits: ⮙8 | Monthly Hits: ⮙13

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1338 - 1340

A Review of Phase Lock Loop Techniques used in Communication Engineering

Piyush Kumar Singh, Bhagwat Kakde

Share this Article

Downloads: 113 | Monthly Hits: ⮙11

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1799 - 1802

Single Phase Clock Distribution using Low Power VLSI Technology

Krishna Naik Dungavath, Dr V. Vijayalakshmi

Share this Article

Downloads: 114 | Weekly Hits: ⮙3

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1441 - 1445

Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology

Rajani Kanta Sutar, M.Jasmin, S. Beulah Hemalatha

Share this Article

Similar Articles with Keyword 'PFD'

Downloads: 111 | Weekly Hits: ⮙3 | Monthly Hits: ⮙11

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 1144 - 1146

Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration

Dr. Manish Sharma, Asma Chishti

Share this Article

Downloads: 114 | Weekly Hits: ⮙3

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1441 - 1445

Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology

Rajani Kanta Sutar, M.Jasmin, S. Beulah Hemalatha

Share this Article

Downloads: 131 | Weekly Hits: ⮙1 | Monthly Hits: ⮙11

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 7 Issue 5, May 2018

Pages: 727 - 732

Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump

Pallavi. K. R, Dr. K. N. Muralidhara

Share this Article

Similar Articles with Keyword 'VCO'

Downloads: 106 | Weekly Hits: ⮙7

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 257 - 260

Low Phase Noise Ring Oscillator Using Current Steering Technique

G. Gopal, Sri M. Madhusudhan Reddy

Share this Article

Downloads: 111 | Weekly Hits: ⮙3 | Monthly Hits: ⮙11

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 1144 - 1146

Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration

Dr. Manish Sharma, Asma Chishti

Share this Article

Downloads: 114 | Weekly Hits: ⮙3

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1441 - 1445

Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology

Rajani Kanta Sutar, M.Jasmin, S. Beulah Hemalatha

Share this Article

Downloads: 122 | Weekly Hits: ⮙2 | Monthly Hits: ⮙9

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 284 - 287

Design of Loop Filter Using CMOS

Sanchita Basu

Share this Article

Downloads: 131 | Weekly Hits: ⮙1 | Monthly Hits: ⮙11

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 7 Issue 5, May 2018

Pages: 727 - 732

Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump

Pallavi. K. R, Dr. K. N. Muralidhara

Share this Article

Similar Articles with Keyword 'FD'

Downloads: 181 | Weekly Hits: ⮙6 | Monthly Hits: ⮙22

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri, Syed Sazad

Share this Article

Downloads: 86 | Weekly Hits: ⮙4 | Monthly Hits: ⮙11

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 7, July 2020

Pages: 576 - 579

Software Loading and Testing Facility for DMC

V. Abinaya, Girish H.

Share this Article

Downloads: 102 | Weekly Hits: ⮙1 | Monthly Hits: ⮙9

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1272 - 1275

Doppler Frequency Effect and BER Performance of FFT Based OFDM System

C Sreevidya, G Sunil

Share this Article

Downloads: 103 | Weekly Hits: ⮙4 | Monthly Hits: ⮙11

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1975 - 1977

Power Reduction Using ACE and NN Schemes

Silpa S Kishore

Share this Article

Downloads: 103 | Weekly Hits: ⮙2 | Monthly Hits: ⮙7

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 6, June 2017

Pages: 1928 - 1931

Comparative Analysis of OFDM Systems based on PAPR Reduction for Cyclic Shifted Partial Transmit Sequence and Conventional Partial Transmit Sequence for Different Shift Values Using different Modulation Schemes

Harshita Soni, Gaurav Gupta

Share this Article



Top