International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064



Research Paper | Electronics & Communication Engineering | India | Volume 7 Issue 4, April 2018

A Dynamic Threshold MOS Logic Based Low Power 8-Bit Pipe Line ADC for Wireless Communications

G. M. Anitha Priyadarshini, Dr. G. A. E. Sathish Kumar

The Most necessary units in wireless communication applications, Broadband transceivers are. Low power and high performance data converters. Therefore the data converters must have less power dissipation, high sampling rate, and resolution. This paper presents a design with low power and high conversion rate Pipe line architecture ADC. The major sub circuits in this design are subtractor, residue amplifier and comparator. These three devices are developed by using Operational. The designed ADC consists of 8 single bit ADCs, i.e each stage having 1-bit resolution, which are designed by using Cadence virtuoso with 180nm technology. The Pipeline architecture and Op amp works with 1.8V supply voltage, and the power dissipation is 11mw

Keywords: ADC, Low power, residue amplifier

Edition: Volume 7 Issue 4, April 2018

Pages: 670 - 673


How to Cite this Article?

G. M. Anitha Priyadarshini, Dr. G. A. E. Sathish Kumar, "A Dynamic Threshold MOS Logic Based Low Power 8-Bit Pipe Line ADC for Wireless Communications", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20181503, Volume 7 Issue 4, April 2018, 670 - 673

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