International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 8, August 2017

Design and Simulation of a Multiport Memory Controller for Communication between Master and Slave Port

Tejaswini A Mahajan, Mahesh Neelagar, T C Thanuja

The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multi-media processing. As the multimedia applications are growing rapidly past a decade. The applications of multi-media for processing high resolution video, data and audio sequences are known to require a high speed and high-density memory port. The memory is required for data storage in real time applications, the memory controllers support DDR3/DDR2/DDR/SDRAM memories and it can be configured according to their requirements. In spite much research on performance improvement, the external memory performance is lagging. Hence the memory controller is essential. The proposed architecture of multiport memory controller is designed for flexible communication between the master and the slave ports and also the communication speed is increased as the design contains a number of buffers for, and also embedded memory for configuration storage and an arbiter including round robin scheduling scheme for scheduling the read/write accesses. The design technique provides flexible systems and independent from other system architecture. The design is modelled in Altera and the read/write simulation results are acquired in Modelsim 6.6a using an external DDR3 SDRAM memory.

Keywords: Altera Quartus II, Buffers, DDR3 SDRAM, Flexible communication, Modelsim 66a

Edition: Volume 6 Issue 8, August 2017

Pages: 1086 - 1089


How to Cite this Article?

Tejaswini A Mahajan, Mahesh Neelagar, T C Thanuja, "Design and Simulation of a Multiport Memory Controller for Communication between Master and Slave Port", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20176119, Volume 6 Issue 8, August 2017, 1086 - 1089

16 PDF Views | 19 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Altera Quartus II'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 8, August 2017

Pages: 1086 - 1089

Design and Simulation of a Multiport Memory Controller for Communication between Master and Slave Port

Tejaswini A Mahajan, Mahesh Neelagar, T C Thanuja

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 84 - 89

High Speed 8-bit Counters using State Excitation Logic and their Application in Frequency Divider

Ranjith Ram. A, Pramod. P

Share this article

Similar Articles with Keyword 'Buffers'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 484 - 488

Interconnect Delay and Power Optimization Using Schmitt Trigger as Alternate Approach to Buffer Insertion

R.S.G.Bhavani, M.Manikumari

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 8, August 2017

Pages: 1086 - 1089

Design and Simulation of a Multiport Memory Controller for Communication between Master and Slave Port

Tejaswini A Mahajan, Mahesh Neelagar, T C Thanuja

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 88 - 90

Dynamic Power Reduction in CMOS Logic Circuits using VID Technique

Preeti Sahu

Share this article

Top