Efficient Design of 1- bit Low Power Full Adder using GDI Technique
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 7, July 2017

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

Deepika Shukla, S.R.P Sinha

The two important issues in designing of analog circuits are area and power which can be controlled by various parameters. Addition is one of the important mathematical operations which serve as a building block. A low power full adder is the important circuit in the designing of other large circuits. In this paper, three low power full adders are designed using basic gate OR, AND, XOR and XNOR. These gates are designed by using GDI technique. When the number of transistors are decreased then the power consumption and area is reduced.GDI is a new technique for low power digital circuits.This techniques reduce the power consumption, propagation delay and transistor count of digital circuits. The adder cell consists of XOR and XNOR gates. The performance of different adder is compared in respect of various parameters. From results, its cleared that the due to less transistor count the power consumption and area is reduced DSCH and MICROWIND tool is used for the circuit design and simulation of it.

Keywords: Low power adder, Gate diffusion technique, full adder, VLSI

Edition: Volume 6 Issue 7, July 2017

Pages: 2073 - 2080

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How to Cite this Article?

Deepika Shukla, S.R.P Sinha, "Efficient Design of 1- bit Low Power Full Adder using GDI Technique", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20175733, Volume 6 Issue 7, July 2017, 2073 - 2080

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