International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 111

Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 7, July 2017


Scan Insertion on Multi Clock Design in Modern SOC's

K. Ramini, B. Bhavani


Abstract: VLSI technology is an emerging field in the current technological due to its advancements in fields of systems architecture, design for testability (DFT) techniques for testing modern digital circuits. DFT techniques are required in order to improve the quality and reduce the test cost of the digital circuit, while at the same time simplifying the test, debug and diagnose tasks. The existing Ad Hoc Approach has the most compact design but takes longer computation time and low-observability. The time critical applications use Structured Approach, Scan design the most widely used structured DFT methodology, attempts to improve testability of a circuit by improving the controllability and observability of storage elements in a sequential design. In this paper different scan architectures are analyzed to study the operation of Full-Scan design. The proposed design includes Full-Scan design using Muxed-D scan cell. Scan control logic is spread across the blocks, based on the scan architecture. Scan enable, scan clocks, length of scan chains, number of EDT channels are required constraints for scan insertion. The Muxed-D scan cell is composed of a D flip-flop and a multiplexer. The designs are synthesized using Synopsys design compiler Software.


Keywords: Design for Testability, Scan Design, Data Input, Scan Input, Scan Enable


Edition: Volume 6 Issue 7, July 2017,


Pages: 1872 - 1877


How to Cite this Article?

K. Ramini, B. Bhavani, "Scan Insertion on Multi Clock Design in Modern SOC's", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=ART20175689, Volume 6 Issue 7, July 2017, 1872 - 1877

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