International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064

Case Studies | Electronics & Communication Engineering | India | Volume 6 Issue 7, July 2017

An Efficient Prototype for Gals Systems in Asynchronous Network-on-Chips through Multiclocking

P. Vijayalakshmi, K. Sathiya

GALS archetype is to partition a system design in decoupled Clock- independent modules. GALS design eliminates the issue of using global clock and decreases area overhead when compared to purely synchronous or purely asynchronous designs. Network- on-chips vigorously benefit to such a globally asynchronous design methodology. Clock free interconnect networks improve authenticity by removing clock-domain passing synchronizations and by using delay-insensitive mediators for solving routing issues. This paper presents an trendsetting methodology for network-on chip Globally- Asynchronous Locally- Synchronous (GALS) system paradigm. High performance multi- clock FPGAs are overburdened for easy and fast prototyping of GALS systems based of an Asynchronous Network-on-Chip (ANoC). Modularity property of asynchronous circuits is fully oppressed to design regular distributed link topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve mediators and synchronization problems. The design is carried out using FPGA and simulation and synthesis reports are shown.

Keywords: GALS - Globaly asynchronous locally synchronous

Edition: Volume 6 Issue 7, July 2017

Pages: 1179 - 1183


How to Cite this Article?

P. Vijayalakshmi, K. Sathiya, "An Efficient Prototype for Gals Systems in Asynchronous Network-on-Chips through Multiclocking", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20175428, Volume 6 Issue 7, July 2017, 1179 - 1183

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