M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 4, April 2017
An Optimized FPGA Implementation of RSD Based ECC Processor
Abstract: Elliptic Curve Cryptography (ECC) is a standout amongst the most interested exploration themes in VLSI. System security is turning out to be increasingly significant as the volume of information being traded on the Internet increments. Point addition and doubling are key operations which choose the Performance of ECC. Here the design with the information way which can perform either prime field G (p) operations or binary field G (2m) operations for arbitrary prime numbers has been proposed. Utilizing this design we can accomplish the high throughput of the both fields that is prime and binary fields. a high throughput modular divider (mod 4n) which results in maximum operating frequency and modular multiplier in the processor is optimized based on throughput and modular reduction. The adder is focused for optimization as the addition is needed for accumulation process in multiplication and division. The Xilinx Virtex 5 field programmable gate array has been utilized.
Keywords: point doubling, Redundant Signed Digit RSD, point addition
Edition: Volume 6 Issue 4, April 2017,
Pages: 2490 - 2494
How to Cite this Article?
M. Rajeswari, M. Vijaya Laxmi, "An Optimized FPGA Implementation of RSD Based ECC Processor", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=ART20172862, Volume 6 Issue 4, April 2017, 2490 - 2494, #ijsrnet
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