International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




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Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 4, April 2017


Low-Power and High?Performance Design Techniques for CMOS 4-bit ALU by using CPL, DPL, DVL

Jagruty Naik


Abstract: High-performance adder, subtractor and multiplier are one of the most fundamental components of ALU. This paper describes low-power, high performance design techniques such as:CPL, DPL, DVL for implementing adder, subtractor and multiplier circuit for achieving improved performance per watt or energy efficiency as well as silicon area efficiency. By considering all these aspect Dual value logic (DVL) is found to be the most energy efficient, high performance design technique which consumes low power, while the Double pass transistor logic (DPL) is shown to improve circuit performance at low supply voltage and Complementary pass-transistor logic (CPL) consume less chip area. By combining these techniques, the addition and subtraction time of a cmos ALU test chip is fabricated in 180 nm using cadence spectra simulator. These circuit design techniques and is capable of an simulation time of 1000ns at a supply voltage of 1.8v.


Keywords: CPL, DPL, DVL, CMOS, figures of merit


Edition: Volume 6 Issue 4, April 2017,


Pages: 1915 - 1919

Low-Power and High?Performance Design Techniques for CMOS 4-bit ALU by using CPL, DPL, DVL


How to Cite this Article?

Jagruty Naik, "Low-Power and High?Performance Design Techniques for CMOS 4-bit ALU by using CPL, DPL, DVL", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=ART20172783, Volume 6 Issue 4, April 2017, 1915 - 1919, #ijsrnet

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