Design and Implementation of High Performance Multiplier Using HDL
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 12, December 2016

Design and Implementation of High Performance Multiplier Using HDL

Prajakta P. Chaure, G. D. Dalvi

This represents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 32 compressors and Radix-8 Booth multiplier with 42 compressors are presented here. The design is structured for m n multiplication where m and n can make up to 126 bits. Carry Look ahead Adder is used as the final adder to enhance the speed of operation. Finally the performance development of the proposed multipliers is validate by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA. The multiplier is an essential element of the digital signal processing such as filtering and convolution. Most digital signal processing methods use nonlinear functions such as discrete cosine transform (DCT) or discrete wavelet transform (DWT). In the majority of digital signal processing (DSP) applications of critical operations are the multiplication and accumulation. In this paper we are implementing the other thing is the real time signal processing required high speed high throughput multiplier. This paper also investigates on various architecture of multiplier and adder which are suitable for throughput signal processing at the same time to achieved low power consumptions developed This project by various systems which are too difficult to implement. But we have design and implement this multiplier with very high performance using booth algorithm. The elements in FPGA which describe the complexity of design, which is reduced considerable. For this system development using wallace tree, carry look ahead adder, which giving high power and reducing the main factor which is time delay. Using this tools and different block we implementing the proper results as shown. So next we described the proposed work and system architecture which is based on booth algorithm and VHDL.

Keywords: FPGA, HDL, Carry Look ahead Adder, Carry Save adder, Wallace Tree, Booth Encoding

Edition: Volume 5 Issue 12, December 2016

Pages: 1648 - 1652

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Prajakta P. Chaure, G. D. Dalvi, "Design and Implementation of High Performance Multiplier Using HDL", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20163828, Volume 5 Issue 12, December 2016, 1648 - 1652

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