Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 12, December 2016

Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder

Nidhi Singh, Mohit Singh

In VLSI design, the performance of any system is determined by the performance of the elements i. e. Multiplier. Multiplier is the slow element in the system. The speed of multiplier depends on multiplication technique and type of adder. This paper proposes the architecture of 16 x 16 high speed binary arithmetic multiplier using Urdhva Tiryagbhyam sutra of Vedic mathematics. Urdhva Tiryagbhyam sutra is used for generating the partial products. The partial product addition in Vedic multiplier is realized using Brent Kung adder. The HDL used for design is Verilog and code is implemented in Xilinx ISE 14.7 software. The combinational path delay of 16x16 bit Vedic multiplier obtained after synthesis is compared with Vedic multiplier using MUX based adder and found that the proposed Vedic multiplier circuit seems to have better performance in terms of speed.

Keywords: Vedic Multiplier, Delay, VLSI, Brent Kung adder, Urdhva Tiryagbhyam Sutra, Verilog HDL

Edition: Volume 5 Issue 12, December 2016

Pages: 239 - 242

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How to Cite this Article?

Nidhi Singh, Mohit Singh, "Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20163395, Volume 5 Issue 12, December 2016, 239 - 242

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