Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 11, November 2016
Design and Implementation of QSD Adder using Quaternary Logic Lookup Table Based on Standard CMOS Technology
Divyasree Pinnamaneni | Nagaraja Kumar Pateti | Dr. M. Gurunadha Babu
Abstract: Multiple-valued logic (MVL) based quaternary look-up-table (QLUT) approach along with QSD adder is proposed in this paper to achieve high performance. The designs in the proposed method are designed to overcome the issues in the existing methods such as extreme power consumption, chip size, delay and increased interconnections in accurate manner. Increasing interconnections and switch resistant based problems in standard CMOS structure are effectively handled by QLUT based clock boosting technique which operates based on MVL. QSD adder is the additional contribution to MVL based QLUT to improve the performance with great reliability. MVL based QLUT-QSD adder approach is valid solution to existing problems. A carry-free arithmetic operation can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD) The Proposed method can improve the time consumption, power consumption and accuracy by exploiting the redundancy. Experimental results reveal that proposed QLUT-QSD adder achieves low computational cost, low power consumption and better accuracy over traditional BLUT.
Keywords: Multiple valued combinational, quaternary look-up-table, QSD carry free adder, Clock boosting technique, Binary look up table
Edition: Volume 5 Issue 11, November 2016,
Pages: 1013 - 1020
How to Cite this Article?
Divyasree Pinnamaneni, Nagaraja Kumar Pateti, Dr. M. Gurunadha Babu, "Design and Implementation of QSD Adder using Quaternary Logic Lookup Table Based on Standard CMOS Technology", International Journal of Science and Research (IJSR), Volume 5 Issue 11, November 2016, pp. 1013-1020, https://www.ijsr.net/get_abstract.php?paper_id=ART20162993
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