Downloads: 133 | Views: 140
Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 9, September 2016
High Speed, Low Power Vedic Multiplier Using Reversible Logic Gate
Sonali S. Kothule | Shekhar H. Bodake 
Abstract: Multipliers are very significantpart of any processor or computing device. More often than not, performance of microcontrollers and DSP processors are calculated on the basis of number of multiplications completed in unit time. Therefore better multiplier architectures are assured to increase the capability of the device. Vedic multiplier is one such auspicious solution. Its easy architecture joined with raised speed forms an unparalleled combination for serving any composite multiplication computations. Attached with these best parts, realizing this with reversible logic further decreases power dissipation. Power dissipation is alternative significant constraint in an embedded system that cannot be ignored. In this paper we introduce a Vedic multiplier known as UrdhvaTiryakbhayam, realized by reversible logic that is the first of its kind. This multiplier may find applications in Fast Fourier Transforms, and additional applications of DSP like software defined radios, imaging, wireless communications.
Keywords: Vedic multiplier, Urdhva Triyagbhyam, Reversible logic, power, delay
Edition: Volume 5 Issue 9, September 2016,
Pages: 570 - 573
Similar Articles with Keyword 'Vedic multiplier'
Downloads: 2 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Student Project, Electronics & Communication Engineering, India, Volume 10 Issue 9, September 2021Pages: 122 - 125
Design of 256 x 256 bit Vedic Multiplier
Aishwarya K M | Dr. Kiran V 
Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020Pages: 1042 - 1046
Renovated 32 Bit ALU Using Hybrid Techniques
Manju Davis | Uma N