Design and Implementation of High Speed and Low Power Consumption FinFET
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 5, May 2017

Design and Implementation of High Speed and Low Power Consumption FinFET

Ragini Soni, Jyotsna Sagar

An application of FinFET Technology has opened new development in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects.

Keywords: DIBL, etches, FinFET, GIDL, hysteretic threshold, Mosfet

Edition: Volume 6 Issue 5, May 2017

Pages: 1133 - 1136

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How to Cite this Article?

Ragini Soni, Jyotsna Sagar, "Design and Implementation of High Speed and Low Power Consumption FinFET", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=9051702, Volume 6 Issue 5, May 2017, 1133 - 1136

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