International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 9, September 2013

Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops

K. Lovaraju, K. Rajendra Prasad

In this paper, a novel low-power pulse-triggered flip-flop (P-FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master slave based FF in the applications of high speed. In particular, digital designs now-a-days often adopt intensive pipelining techniques and employ many FF-rich Modules. It is also estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20 %45 % of the total system power. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. The simulations are done using Microwind & DSCH analysis software tools. Our proposed system simulations are done under 50nm technology and the results are compared with other conventional flip-flops. Hence, our proposed system is showing better output than the other flip-flops.

Keywords: DSCH, Flip-Flop, low power, Microwind, Pulse triggered

Edition: Volume 2 Issue 9, September 2013

Pages: 80 - 83


How to Cite this Article?

K. Lovaraju, K. Rajendra Prasad, "Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=31081303, Volume 2 Issue 9, September 2013, 80 - 83

27 PDF Views | 21 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'DSCH'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 2723 - 2728

An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating

Bhima Venkata Sujatha, V. T. Venkateswarlu

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 7, July 2017

Pages: 2073 - 2080

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

Deepika Shukla, S.R.P Sinha

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 80 - 83

Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops

K. Lovaraju, K. Rajendra Prasad

Share this article

Similar Articles with Keyword 'Flip-Flop'

Comparative Studies, Electronics & Communication Engineering, India, Volume 5 Issue 8, August 2016

Pages: 1586 - 1590

Comparative Analysis of D Flip-Flops in Terms of Propagation Delay

Anu Samanta, Madhu Sudan Das

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2799 - 2802

Analysis of Low Power Pulse Triggered Flip Flop

Deepika Goyal

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 2723 - 2728

An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating

Bhima Venkata Sujatha, V. T. Venkateswarlu

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 1346 - 1349

Razor Based Low-Power Multiplier with Variable Latency Design

Sagar Latti, T C Thanuja

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 4, April 2013

Pages: 183 - 187

A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement

Shakthipriya.R, Kirthika.N

Share this article

Similar Articles with Keyword 'low power'

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh, Dr. Subodh Wairya

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2737 - 2741

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 2657 - 2661

Empirical Study of Incorporation of SET and Hybrid CMOS-SET in Decision Making Sub-Systems

Jayanta Gope, Aloke Raj Sarkar

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2476 - 2479

Software Defined Radio Signal Detector Implementation using FPGA

Rohan Fernandes, Shubhangi Mahamuni

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1332 - 1335

Low Power Self-Timed TCAM Based on Overlapped Search Mechanism with IP Filter Implementation

Jerrin Paul M, Hazel Elsa John

Share this article

Similar Articles with Keyword 'Microwind'

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 6, June 2017

Pages: 1751 - 1756

Minimization of Leakage Current of 6T SRAM using Optimal Technology

Sumit Kumar Srivastava, Amit Kumar

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2221 - 2224

Implementation of Low Power Ternary Logic Gates using CMOS Technology

V. T. Gaikwad, Dr. P. R. Deshmukh

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 2723 - 2728

An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating

Bhima Venkata Sujatha, V. T. Venkateswarlu

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 7, July 2017

Pages: 2073 - 2080

Efficient Design of 1- bit Low Power Full Adder using GDI Technique

Deepika Shukla, S.R.P Sinha

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 80 - 83

Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops

K. Lovaraju, K. Rajendra Prasad

Share this article

Similar Articles with Keyword 'Pulse triggered'

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2799 - 2802

Analysis of Low Power Pulse Triggered Flip Flop

Deepika Goyal

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 4, April 2013

Pages: 183 - 187

A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement

Shakthipriya.R, Kirthika.N

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 9, September 2013

Pages: 80 - 83

Design and Analysis of Low Power Implicit Pulse Triggered Flip-Flops

K. Lovaraju, K. Rajendra Prasad

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 2158 - 2160

Analysis of Implicit Type Pulse Triggered Flip Flop

Richa Srivastav, Dinesh Chandra, Sumit Khandelwal

Share this article

Top