Design of High Speed Digital CMOS Comparator Using Parallel Prefix Tree
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 10, October 2015

Design of High Speed Digital CMOS Comparator Using Parallel Prefix Tree

N. Prasanna, H. Sumitha

This paper Presents a new comparator design is proposed by using parallel prefix tree. Energy efficient and high speed operation of comparators is needed for high speed digital circuits. The comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. In existing system, the parallel prefix structure is designed for 16, 32 and 64 bit architectures and the reports from the Xilinx tool concludes that for every bit range doubles the delay, memory, LUT and power has not doubled up to the mark. But In the proposed design of my project, each and every element in the parallel prefix structure will be replaced by universal logic (multiplexer). By performing this modification in the architecture will leads to reduction in POWER CONSUMPTION and DELAY. Parallel prefix tree structure high fan in, high fan out, Bitwise competition logic (BCL).

Keywords: copy/paste

Edition: Volume 4 Issue 10, October 2015

Pages: 204 - 207

Share this Article

How to Cite this Article?

N. Prasanna, H. Sumitha, "Design of High Speed Digital CMOS Comparator Using Parallel Prefix Tree", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=29091501, Volume 4 Issue 10, October 2015, 204 - 207

106 PDF Views | 89 PDF Downloads

Download Article PDF



Top