FPGA Implementation of SRRC Filter for WCDMA Systems
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

FPGA Implementation of SRRC Filter for WCDMA Systems

K. Pavan Kumar, Sri T. Thammi Reddy

This paper presents the FPGA implementation of Square root raised cosine filter for pulse shaping used in WCDMA systems. Square root raised cosine filter is a FIR filter. Square root raised cosine filters are used in both transmitter and receiver for matching filter purpose. Mainly square root raised cosine filter is used for pulse shaping so that it reduces the required system bandwidth and also reduces inter symbol interference. SRRC filter also designed to maintain the power level in dbs. SRRC filter is designed by five levels of adders with a roll off factor 0.2.Shifting and add method is used for designing of SRRC filter.

Keywords: SRRC filter, FIR filter, Inter symbol interference, Pulse shaping, Roll off factor, WCDMA systems

Edition: Volume 4 Issue 7, July 2015

Pages: 2581 - 2584

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How to Cite this Article?

K. Pavan Kumar, Sri T. Thammi Reddy, "FPGA Implementation of SRRC Filter for WCDMA Systems", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=26071501, Volume 4 Issue 7, July 2015, 2581 - 2584

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