FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Views: 142 , Downloads: 122 | CTR: 86 % | Weekly Popularity: ⮙7

Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 9, September 2017

FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm

B. Sai Reddy, V. Seetha Rama Rao

Communication system transmits data from source to transmitter through a channel or medium such as wired or wireless. The efficiency of received data depends on medium and noise. LDPC codes are used to correct the errors by adding redundant symbols to the original data called as Error Correction Codes (ECCs).Without ECCs data need to retransmit if it could detect there is an error in the received data. ECC are also called as forward error correction (FEC) as we can correct bits without retransmission. ECCs are really helpful for high speed and long distance Communication LDPC consist of mainly Encoder and Decoder blocks, AWGN channel, Detector. These blocks are designed by using Verilog HDL with Xilinx ISE Design suite 12.4 version tool. The designs implemented in Xilinx SPARTAN 3E XC3S500EFG320 FPGA board.

Keywords: HDL, Error Correction Codes, ISE, AWGN

Edition: Volume 6 Issue 9, September 2017

Pages: 1683 - 1690

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How to Cite this Article?

B. Sai Reddy, V. Seetha Rama Rao, "FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=22091704, Volume 6 Issue 9, September 2017, 1683 - 1690

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