International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064


Downloads: 108

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014


Efficient Pipelined FPGA Implementation of Steerable Gaussian Smoothing Filter

Shraddha Barbole, Dr. Sanjeevani Shah


Abstract: Smoothing filters have wide area of applications such as image and video analysis, which extends to edge detection, motion analysis, line parameter estimation, and texture analysis. To achieve smoothing, it is essential to have directional smoothing filters which can be oriented in any arbitrary direction. For real time applications, hardware devices having capability of parallel processing can be used. The steerability is the property, in which several filtering operations outputs are linearly combined to achieve output of a directional filter which is arbitrarily oriented. Though the literature describes the several efficient FPGA implementations of the convolution operation for non-separable and separable, limited work is available related to steerable filter implementations. In this system, steerable Gaussian smoothing filters are implemented on an FPGA platform using Virtex-V ML506 evaluation board. The output is displayed on VGA display. The algorithm uses delaying of intermediate outputs which reduces memory requirements. This allows simultaneous implementation of both horizontal and vertical convolution. Due to pipelined approach, memory resources and other device utilization is reduced. The key advantages of FPGAs over DSP implementations include integration, performance and customization using design techniques of parallel and pipeline operations. A pipelined approach of convolution gives the less number of resources.


Keywords: Steerability, Virtex-V, Parallel Processing, Pipelined Approach


Edition: Volume 3 Issue 8, August 2014,


Pages: 1753 - 1758


How to Cite this Article?

Shraddha Barbole, Dr. Sanjeevani Shah, "Efficient Pipelined FPGA Implementation of Steerable Gaussian Smoothing Filter ", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=2015914, Volume 3 Issue 8, August 2014, 1753 - 1758

How to Share this Article?

Enter Your Email Address


Similar Articles with Keyword 'Parallel Processing'

Downloads: 112

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 909 - 913

Implementation of 100BASE-T4 Network Repeater Using FPGA

Sudarshan M. Dighade, Pranav P. Kulkarni

Share this Article

Downloads: 122

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 735 - 739

Design and Implementation of Convolutional Encoder and Parallel Processing Viterbi Decoder Using Verilog

Vinay.B.K, Sunil.M.P

Share this Article
Top