ARM Advanced High-Performance Bus Complaint Inter Integrated Circuit
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

ARM Advanced High-Performance Bus Complaint Inter Integrated Circuit

Prabhakar. K, Gowda. R. M. C.

This paper implements is an novel approach to enable data transfer between two bus architectures, AHB and I2C which have different functionalities and characteristics. The coding for this module is designed in the Verilog HDL (IEEE Std 2001) and simulated in Model sim 10.1C. This module includes both design and verification phases. The Communication is done with AHB as Master and I2C as Slave, hence achieve error free data transfer between the two bus architectures. This implementation includes one Master and two Slaves. It can further extended to many Slaves. It can be used to read & write registers of the connected device, accessing low speed ADCs and DACs, controlling LED & LCD displays.

Keywords: : AHB, I2C, wrapper, master, slave, wishbone core

Edition: Volume 3 Issue 7, July 2014

Pages: 2125 - 2128

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How to Cite this Article?

Prabhakar. K, Gowda. R. M. C., "ARM Advanced High-Performance Bus Complaint Inter Integrated Circuit", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=201581, Volume 3 Issue 7, July 2014, 2125 - 2128

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