Design and Simulation of SPI Master / Slave Using Verilog HDL
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014

Design and Simulation of SPI Master / Slave Using Verilog HDL

T. Durga Prasad, B. Ramesh Babu

The object of this paper is to design and simulation of SPI (serial peripheral interface) master and slave using verilog HDL. The SPI (serial peripheral interface) is a kind of serial communication protocol. It transfers synchronous serial data in full duplex mode. The SPI is commonly used for communications between Integrated Circuits for communication with On-Board Peripherals. The SPI communicate in two modes master and slave. Where the master device generates serial clock and multiple slave devices are allowed with individual salve select lines. And the whole design is simulated and synthesized with Xilinx ISE design suite 13.2.

Keywords: SPI serial peripheral interface, Verilog HDL

Edition: Volume 3 Issue 8, August 2014

Pages: 1363 - 1365

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How to Cite this Article?

T. Durga Prasad, B. Ramesh Babu, "Design and Simulation of SPI Master / Slave Using Verilog HDL", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2015624, Volume 3 Issue 8, August 2014, 1363 - 1365

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