Leakage Power Reduction in 5-Bit Full Adder using Keeper & Footer Transistor
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014

Leakage Power Reduction in 5-Bit Full Adder using Keeper & Footer Transistor

Narendra Yadav, Vipin Kumar Gupta

In the present scenario Power consumption plays an imperative role specifically in the field of VLSI. Every designer, either an analog circuit or a digital circuit designer is concerned about the amount of the power a circuit is going to consume in the end. The main objective of this project is to design and implement of the leakage power reduction in 5-bit Full Adder (Domino Logic and Transmission Gate) technology using of footer and Keeper transistor. Keeper and Footer transistor using Transmission gate or Domino Logic are used to cooperate in reduction static power dissipation in 5-Bit Full Adder. There is reduction of 72.18 % in power consumption by 5-bit transmission gate full adder with footer transistor as compared to 5-bit full adder on Tanner Tools.

Keywords: Domino Logic Style, Keeper transistor, Footer transistor, Transmission Gate, Feedback

Edition: Volume 3 Issue 8, August 2014

Pages: 1100 - 1104

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How to Cite this Article?

Narendra Yadav, Vipin Kumar Gupta, "Leakage Power Reduction in 5-Bit Full Adder using Keeper & Footer Transistor", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2015572, Volume 3 Issue 8, August 2014, 1100 - 1104

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