Abstract of Design & Analysis of Modified Conditional Data Map
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064

Downloads: 122

Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

Design & Analysis of Modified Conditional Data Mapping Flip-Flop to Ultra Low Power and High Speed Applications

Soni Singh, Himani Mittal

In the history, the major issues of the VLSI designer were area, cost, performance, and reliability; power concern was typically of only lesser importance. But more than the last few years power in the circuit is the major difficulty at the present days which is being faced by the very large scale integration industries. The power dissipation in several circuits is typically take place by the clocking system which includes the clock distribution system and sequential elements (flip flops and latches) in it. The quantity of power dissipation by any clock distribution system and sequential circuit in any chip is as regards of 30 % to 60 % of the overall chip power dissipation by the circuit. Clock is the most vital signal present in the chip. Clock signals are synchronizing signals which offer timing references for computation of in the least work in synchronous digital systems. In this paper the power of the sequential circuit is reduced which in position reduce the on the whole power of the chip. Here dissimilar low power techniques for the lowering static power dissipation are second-hand in the sequential circuit are surveyed. The work analyses the power consumption and propagation delay of flip- flop designs. In Tanner 14.0m CMOS technology designs are implemented.

Keywords: Flip-flop, Low power, CMOS Circuit, delay optimization

Edition: Volume 3 Issue 7, July 2014

Pages: 2409 - 2413

Share this Article

How to Cite this Article?

Soni Singh, Himani Mittal, "Design & Analysis of Modified Conditional Data Mapping Flip-Flop to Ultra Low Power and High Speed Applications", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=201526, Volume 3 Issue 7, July 2014, 2409 - 2413

Enter Your Email Address


Similar Articles with Keyword 'Flipflop'

Downloads: 114

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1677 - 1680

An Area Efficient Approach on PACC RLE Encoder

Ancy Mathew, Rafeekha M J

Share this Article

Downloads: 144

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 2, February 2017

Pages: 321 - 325

A Novel Adaptive Technique to Mitigate Radiation Effects on FPGAS

T. Mary Daphne, Dr. T. Latha

Share this Article

Similar Articles with Keyword 'Low power'

Downloads: 185 | Monthly Hits: ⮙1

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri, Syed Sazad

Share this Article

Downloads: 1 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Student Project, Electronics & Communication Engineering, India, Volume 10 Issue 9, September 2021

Pages: 122 - 125

Design of 256 x 256 bit Vedic Multiplier

Aishwarya K M, Dr. Kiran V

Share this Article

Similar Articles with Keyword 'CMOS Circuit'

Downloads: 108

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article

Downloads: 115

Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1324 - 1330

A Survey on Analytical Delay Models for CMOS Inverter-Transmission Gate Structure

Sreelakshmi V., Dr. K. Gnana Sheela

Share this Article
Top