Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014
Design & Analysis of Modified Conditional Data Mapping Flip-Flop to Ultra Low Power and High Speed Applications
Soni Singh, Himani Mittal
In the history, the major issues of the VLSI designer were area, cost, performance, and reliability; power concern was typically of only lesser importance. But more than the last few years power in the circuit is the major difficulty at the present days which is being faced by the very large scale integration industries. The power dissipation in several circuits is typically take place by the clocking system which includes the clock distribution system and sequential elements (flip flops and latches) in it. The quantity of power dissipation by any clock distribution system and sequential circuit in any chip is as regards of 30 % to 60 % of the overall chip power dissipation by the circuit. Clock is the most vital signal present in the chip. Clock signals are synchronizing signals which offer timing references for computation of in the least work in synchronous digital systems. In this paper the power of the sequential circuit is reduced which in position reduce the on the whole power of the chip. Here dissimilar low power techniques for the lowering static power dissipation are second-hand in the sequential circuit are surveyed. The work analyses the power consumption and propagation delay of flip- flop designs. In Tanner 14.0m CMOS technology designs are implemented.
Keywords: Flip-flop, Low power, CMOS Circuit, delay optimization
Edition: Volume 3 Issue 7, July 2014
Pages: 2409 - 2413
How to Cite this Article?
Soni Singh, Himani Mittal, "Design & Analysis of Modified Conditional Data Mapping Flip-Flop to Ultra Low Power and High Speed Applications", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=201526, Volume 3 Issue 7, July 2014, 2409 - 2413
121 PDF Views | 106 PDF Downloads
Similar Articles with Keyword 'Flip-flop'
Analysis of Low Power Pulse Triggered Flip Flop
Razor Based Low-Power Multiplier with Variable Latency Design
Sagar Latti, T C Thanuja
Scan Insertion on Multi Clock Design in Modern SOC?s
K. Ramini, B. Bhavani
An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating
Bhima Venkata Sujatha, V. T. Venkateswarlu
Comparative Analysis of D Flip-Flops in Terms of Propagation Delay
Anu Samanta, Madhu Sudan Das
Similar Articles with Keyword 'Low power'
Realization of Smart City Using 5G Cognitive Radio
Lalit Chettri, Syed Sazad
Communication of Multi Mobile-Robots Based On ZigBee Network
Taskeen Sultana, Zeenath
A Fast-Locking All-Digital Deskew Buffer with DCC using Digital-Controlled Delay Line
A.Ashwini, H. Shravan Kumar
Low Phase Noise Ring Oscillator Using Current Steering Technique
G. Gopal, Sri M. Madhusudhan Reddy
Low Power Spectral Analysis for Built in Self Test by Using System on Chip
L. Maheswari, B. V. P. Prasad
Similar Articles with Keyword 'CMOS Circuit'
Design of Advanced Configurable Radix-4 Booth Multiplier for Low Power and High Speed Applications
Sareddy Swathi, P. Sandhya Rani
A Survey on Analytical Delay Models for CMOS Inverter-Transmission Gate Structure
Sreelakshmi V., Dr. K. Gnana Sheela
Review on Different Types of Power Efficient Adiabatic Logics
Vijendra Pratap Singh, Dr. S.R.P Sinha
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
K. Swarna Madhuri, M. Madhu Sudhan Reddy
Design and Analysis of f2g Gate using Adiabatic Technique