International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064




Downloads: 135

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014


Dynamic Power Reduction in CMOS Logic Circuits using VID Technique

Preeti Sahu


Abstract: VID is a new technique for complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. Here demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. We obtained a power saving of 58 % over an un-optimized design. The optimized circuits had the same critical path delays as their original un-optimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.


Keywords: Introduction, Background, Previous work with Variable Input Delay, Dynamic Power reduction, Experimental Analysis, Conclusion


Edition: Volume 3 Issue 8, August 2014,


Pages: 88 - 90


How to Cite this Article?

Preeti Sahu, "Dynamic Power Reduction in CMOS Logic Circuits using VID Technique", International Journal of Science and Research (IJSR), Volume 3 Issue 8, August 2014, pp. 88-90, https://www.ijsr.net/get_abstract.php?paper_id=2015185

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