International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 113

Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014


Digital Multipliers: A Review

Jyoti Sharma [10] | Sachin Kumar [11]


Abstract: Multiplication is one of the basic functions used in digital signal processing (DSP). Hardware resources and processing time required by it are more than addition and subtraction. There are two kinds of multiplication algorithms; serial multiplication algorithms and parallel Multiplication algorithms. Serial multiplication algorithms use sequential circuits with feedbacks. Parallel multiplication algorithms often use combinational circuits; and do not contain feedback structures. This paper presents various multiplier architectures. Multiplier architectures fall generally into two categories i. e. ; tree multipliers and array multipliers. Tree multipliers add as many partial products in parallel as possible and therefore; are very high performance architectures. Multiplication operation involves generation of partial products and their accumulation. The speed of multiplication can be increased by reducing the number of partial products.


Keywords: Architecture, Digital system, Hardware, Logic functions, Propagation delay, Sequentially


Edition: Volume 3 Issue 6, June 2014,


Pages: 741 - 743

Digital Multipliers: A Review


How to Cite this Article?

Jyoti Sharma, Sachin Kumar, "Digital Multipliers: A Review", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=201483, Volume 3 Issue 6, June 2014, 741 - 743, #ijsrnet

How to Share this Article?

Enter Your Email Address




Similar Articles with Keyword 'Architecture'

Downloads: 193

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri | Syed Sazad [2]

Share this Article

Downloads: 127 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article


Top