Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014
A New Approach for Faster and Size Efficient Signed Multiplier of 8bits
Monika Raghav | Rakesh Jain 
Abstract: : Multiplier is one of the essential element for microprocessors ; digital signal processors etc. In this paper; we designed and implemented a new high speed 8 bit signed multiplier. This paper presents an efficient implementation of high speed multiplier using the shift and add method; using Booth algorithm. This proposed architecture is implemented by using the radix-4 booth recoding process. The proposed multiplier reduces the partial product array by almost 1/2th the size of the bits. This reduction in partial product increases the speed of the multiplier. The proposed multiplier is compared with the former method of multipliers; it demonstrated that it is more efficient in the the term of delay and area. The proposed multiplier is designed and implemented using verilog HDL in XILINX 9.2 version. The result of conventional multiplier are compared with proposed multiplier. Experimental results demonstrate that the proposed multiplier has 26.13 % faster than conventional signed multiplier and size also reduces 33 %. The proposed method can be extended to any higher radix encodings; as well as to any size square and rectangular multipliers.
Keywords: signed multiplier, Radix-4 multiplier, Radix-8 multiplier, Baugh-Wooley BW algorithm, Verilog, FPGA
Edition: Volume 3 Issue 6, June 2014,
Pages: 2740 - 2744
How to Cite this Article?
Monika Raghav, Rakesh Jain, "A New Approach for Faster and Size Efficient Signed Multiplier of 8bits", International Journal of Science and Research (IJSR), Volume 3 Issue 6, June 2014, pp. 2740-2744, https://www.ijsr.net/get_abstract.php?paper_id=2014828
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