Simulation of Different bit Carry-Skip Adder in Verilog
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Case Studies | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014

Simulation of Different bit Carry-Skip Adder in Verilog

Sangeeta Rani, Sachin Kumar

Adders are the most basic and essential component used in Digital signal processing and is widely used in the digital integrated circuits. As there are various adder structures which provide the increased operational speed in the arithmetic circuits but in terms of area or delay there is a loose connection (area or delay of the adder circuit design is more as compared to the other structures discovered). With the advances in technology; researchers have tried and are trying to design adders which offer either high speed; low power consumption; less area or the combination of them. The addition of the two bits is very based on the various speed-up schemes for binary addition; a comprehensive overview and different bits carry skip adder structures is given in this paper. We will synthesize the Carry skip adder of bits 4 Bit; 8 Bit; 16 Bit and 32 Bit in ISE XIILINX 10.1 by using HDL - Verilog and will simulate them in Modelsim 6.4a. Also Delay; Slices Used and Look up tables used by the Different bit Carry skip adder structure is given.

Keywords: Carry skip adder, Ripple Carry Adder, Carry Look Ahead adder, Carry Save adder

Edition: Volume 3 Issue 6, June 2014

Pages: 2343 - 2346

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How to Cite this Article?

Sangeeta Rani, Sachin Kumar, "Simulation of Different bit Carry-Skip Adder in Verilog", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2014788, Volume 3 Issue 6, June 2014, 2343 - 2346

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