M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014
An Efficient High Speed Convolution Encoder and Viterbi Decoder
Chandan Nagraj | S Muralinarasimham
Abstract: The main aim of the project is execution of convolution encoder and Viterbi decoder by applying HDL (Verilog) coding. The overall objective is to clearly understand in depth the convolution encoder and Viterbi Decoder model; to evaluate the basic functionalities and steps involved in the process; through HDL code and finally to critically analyze the results obtained through HDL code. The main purpose of this study is to yield the gains obtained by the developers with the usage of convolution encoder and Viterbi decoder. Here; we make use of HDL code in order to implement the both encoder and decoder in a simpler way so that we can achieve faster operation. Convolutional codes are non-blocking codes that can be designed to either error detecting or correcting. Convolution coding has been used in communication systems including deep space communication and wireless communication. At the receiver end the original message sequence is obtained from the received data using Viterbi decoder; by making use of trellis diagram. This project helps the students related to the communications and also it helps the people who are in the field of encoders and decoders as it is one of the efficient methods for reducing the errors while communication procedure is in advance.
Keywords: HDL, Verilog, Convolution encoder, Viterbi decoder, trellis diagram
Edition: Volume 3 Issue 6, June 2014,
Pages: 1474 - 1478
How to Cite this Article?
Chandan Nagraj, S Muralinarasimham, "An Efficient High Speed Convolution Encoder and Viterbi Decoder", International Journal of Science and Research (IJSR), Volume 3 Issue 6, June 2014, pp. 1474-1478, https://www.ijsr.net/get_abstract.php?paper_id=2014554
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