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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014
Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops
Nemitha B, Pradeep Kumar B. P
In this paper the Performance of body biased True Single Phase Clock (BBTSPC) and body biased Extended True Single Phase Clock (BBETSPC) are investigated. The delay of BBTSPC and BBETSPC are analyzed; simulated and compared with the existing TSPC and ETSPC. A high speed divide-by-2/3 unit of prescaler with the body biased is proposed and validated that this prescaler can operate with higher frequency of 4 GHz stably on a 180 nm technology. This prescaler with the body bias design can be widely used in Communication data analysis probe systems.
Keywords: CMOS integrated circuit, D ip-op DFF, frequency divider, frequency synthesizer, high-speed digital circuit, phase-locked loops PLLs, true single-phase clock TSPC
Edition: Volume 3 Issue 6, June 2014
Pages: 847 - 850
How to Cite this Article?
Nemitha B, Pradeep Kumar B. P, "Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2014316, Volume 3 Issue 6, June 2014, 847 - 850
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