Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Deepak P. Jose, C. P Sureshkumar

Clock distribution networks forms an inherent part of any digital circuit. It use a large part of the total circuit power, which is not worthy. Different techniques are employed up till now to reduce the clock power. In this paper we have to demonstrate how clock power can be reduced significantly by distributing it at reduced supply voltage and analyse the power consumption of clock distribution network with different frequencies like 100 MHz, 200 MHz, 250 MHz, 400 MHz, and 1 GHz etc. The clock distribution network is designed and simulated in 180 nm technology. Achieving power reduction of about 52 %, 48 %, 44 %, 38 %, 27 %and26 %respectively

Keywords: Low-power design, voltage scaling, clock networks, VLSI Very Large Scale Integration

Edition: Volume 3 Issue 7, July 2014

Pages: 1386 - 1390

Share this Article

How to Cite this Article?

Deepak P. Jose, C. P Sureshkumar, "Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20141239, Volume 3 Issue 7, July 2014, 1386 - 1390

117 PDF Views | 96 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Low-power design'

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1386 - 1390

Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Deepak P. Jose, C. P Sureshkumar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 580 - 587

Study and Analysis of Different Parameters and Power Consumption of Various Multipliers in FIR Filter using VHDL

Sushant Shekhar, Ghanshyam Jangid

Share this Article

Similar Articles with Keyword 'voltage scaling'

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1386 - 1390

Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Deepak P. Jose, C. P Sureshkumar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 987 - 991

Wide Range Enable Level Shifter for Multi-Supply Voltage Designs

Puneet Patil, D Sheshachalam

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1118 - 1124

Improved Power Reduction and Aging Mitigation Using Gate Replacement and Voltage Scaling Techniques

Jibi K Kurian, Praveena S Kammath

Share this Article

Similar Articles with Keyword 'VLSI Very Large Scale Integration'

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1386 - 1390

Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Deepak P. Jose, C. P Sureshkumar

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 151 - 154

Implementation of Delay Measurement System for Small Delay Defect Detection

Supriya Thorat, Snehal Bhosale

Share this Article
Top