Comparative Studies | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014
Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology
Umashankar Dhepra, Rajkumar Gehlot
Power consumption has emerged as a primary design constraint for today VLSI integrated circuits (ICs). AS per reducing Technology, mostly Nanometer technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU. In this paper we introduced low power consume one-bit full adders, including the most motivating of those are analyzed and compared for speed, leakage power, and leakage current. The simulation has been carried out on a Cadence environment virtuoso tool using a 0.45-m technology
Keywords: VLSI, CMOS, Full Adder, leakage current, process invariance and circuit invariance
Edition: Volume 3 Issue 7, July 2014
Pages: 764 - 767
How to Cite this Article?
Umashankar Dhepra, Rajkumar Gehlot, "Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20141136, Volume 3 Issue 7, July 2014, 764 - 767
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