Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Views: 138 , Downloads: 108 | CTR: 78 % | Weekly Popularity: ⮙2

Comparative Studies | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology

Umashankar Dhepra, Rajkumar Gehlot

Power consumption has emerged as a primary design constraint for today VLSI integrated circuits (ICs). AS per reducing Technology, mostly Nanometer technology regime, leakage power has become a major component of total power. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU. In this paper we introduced low power consume one-bit full adders, including the most motivating of those are analyzed and compared for speed, leakage power, and leakage current. The simulation has been carried out on a Cadence environment virtuoso tool using a 0.45-m technology

Keywords: VLSI, CMOS, Full Adder, leakage current, process invariance and circuit invariance

Edition: Volume 3 Issue 7, July 2014

Pages: 764 - 767

Share this Article

How to Cite this Article?

Umashankar Dhepra, Rajkumar Gehlot, "Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20141136, Volume 3 Issue 7, July 2014, 764 - 767

138 PDF Views | 108 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'VLSI'

Views: 61 , Downloads: 50 | CTR: 82 % | Weekly Popularity: ⮙6

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 3, March 2021

Pages: 143 - 150

VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem

Ragi R G, Jayaraj U Kidav, Roshith K

Share this Article

Views: 121 , Downloads: 97 | CTR: 80 %

Review Papers, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2313 - 2315

Review of Fully Reused VLSI Architecture of Channel Encoding Using SOLS Technique for DSRC Applications

Supriya S. Garade, P. R. Badadapure

Share this Article

Views: 144 , Downloads: 100 | CTR: 69 % | Weekly Popularity: ⮙4

Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1097 - 1102

A Survey on an VLSI Based Data Transfer Schemes

Saiju Lukose, Gnana Sheela K

Share this Article

Views: 123 , Downloads: 100 | CTR: 81 % | Weekly Popularity: ⮙2

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 903 - 904

VLSI Design in Terms of Power System

Bhawana Singh, Nidhi Goyal

Share this Article

Views: 139 , Downloads: 101 | CTR: 73 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2561 - 2564

Statistical Simulation for BIST Architecture using Cognitive Principles

Shradha Khemka

Share this Article

Similar Articles with Keyword 'CMOS'

Views: 182 , Downloads: 90 | CTR: 49 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article

Views: 122 , Downloads: 97 | CTR: 80 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, Sudan, Volume 3 Issue 7, July 2014

Pages: 1756 - 1759

Verification of a Readout Design for Multiple Energy Discrimination working in Single Photon Processing Pixel Array

Suliman Abdalla, Bengt Oelmman, Amin Babiker

Share this Article

Views: 140 , Downloads: 101 | CTR: 72 %

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this Article

Views: 137 , Downloads: 103 | CTR: 75 % | Weekly Popularity: ⮙4

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 671 - 674

A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18?m CMOS Technology

Bharti D.Chaudhari, Priyesh P. Gandhi

Share this Article

Views: 140 , Downloads: 103 | CTR: 74 % | Weekly Popularity: ⮙5

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 847 - 850

Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops

Nemitha B, Pradeep Kumar B. P

Share this Article

Similar Articles with Keyword 'Full Adder'

Views: 134 , Downloads: 104 | CTR: 78 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Views: 125 , Downloads: 105 | CTR: 84 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 2276 - 2280

Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Subhag Yadav, Vipul Bhatnagar

Share this Article

Views: 133 , Downloads: 105 | CTR: 79 % | Weekly Popularity: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2827 - 2831

Analysis of Modified Hybrid Full Adder with High Speed

Jigyasa, Kumar Saurabh

Share this Article

Views: 126 , Downloads: 107 | CTR: 85 % | Weekly Popularity: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 2383 - 2388

Design and Analysis of Dynamic Current Mode Full Adder with reduced Power and Delay

Dr. S.R.P. Sinha, Namita Tiwari

Share this Article

Views: 138 , Downloads: 108 | CTR: 78 % | Weekly Popularity: ⮙2

Comparative Studies, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 764 - 767

Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology

Umashankar Dhepra, Rajkumar Gehlot

Share this Article

Similar Articles with Keyword 'leakage current'

Views: 140 , Downloads: 101 | CTR: 72 %

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this Article

Views: 130 , Downloads: 107 | CTR: 82 %

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 11, November 2017

Pages: 2142 - 2145

Novel Design of Low Power Nonvolatile 10T1R SRAM Cell

Vani Tripathi, Bhawna Trivedi

Share this Article

Views: 138 , Downloads: 108 | CTR: 78 % | Weekly Popularity: ⮙2

Comparative Studies, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 764 - 767

Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology

Umashankar Dhepra, Rajkumar Gehlot

Share this Article

Views: 135 , Downloads: 108 | CTR: 80 % | Weekly Popularity: ⮙3

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1043 - 1047

Complementary Metal-Oxide Semiconductor: A Review

Komal Rohilla, Ritu Pahwa, Shaifali Ruhil

Share this Article

Views: 124 , Downloads: 108 | CTR: 87 % | Weekly Popularity: ⮙4

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 7 Issue 1, January 2018

Pages: 1367 - 1371

Reduction of Current Collapse and Leakage Current in AlGaN/GaN Double Channel HEMT

Sarita Gangwar

Share this Article
Top