Abstract: Low Power Circuit Design Using Positive Feedback Adiabatic Logic
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064

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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014

Low Power Circuit Design Using Positive Feedback Adiabatic Logic

Arjun Mishra, Neha Singh

This paper presents an adiabatic logic family called positive feedback adiabatic logic circuits (PFAL). There is power reduction due to energy recovery in the recovery phase of the clock supply. The power dissipation comparison with the static CMOS logic is performed. The simulation is performed on cadence virtusuo using 180nm CMOS technology. The result shows that power reduction of 50 % to 70 % can be achieved over static CMOS within a practical operating frequency range.

Keywords: Adiabatic, CMOS, PFAL, ECRL, N-MOS, P-MOS

Edition: Volume 3 Issue 6, June 2014

Pages: 43 - 45

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How to Cite this Article?

Arjun Mishra, Neha Singh, "Low Power Circuit Design Using Positive Feedback Adiabatic Logic", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2014110, Volume 3 Issue 6, June 2014, 43 - 45

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