Area and Delay Minimization of Radix-2k Feedforward FFT Architecture
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 5, May 2014

Area and Delay Minimization of Radix-2k Feedforward FFT Architecture

A. Salai Kishwar Jahan, A. Indhumathi

The radix-2 was a milestone in the design of pipelined FFT hardware architectures. Later; radix-2 extended to radix-216.However; radix-216 was only proposed for single path delay feedback (SFD) architectures; but not for feedforward; also it called multi path delay commutator (MDC).The radix-216 feedforward Fast Fourier Transform architecture (FFT).In feedforward architectures radix-216 can be used for any number of parallel samples which is a power of two. Furthermore; both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this; the designs can achieve very high throughputs and reduce the spare complexity; which make them suitable for the most demanding applications. Indeed; the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones; also called multi path delay feedback (MDF) ; when several samples in parallel must be processed. As result; the proposed radix-216 feedforward architectures not only offer an attractive solution for current applications; but also open up a new research line on feedforward structures.

Keywords: Fast Fourier Transform, Multi path delay feedback MDF, Pipelined Architecture

Edition: Volume 3 Issue 5, May 2014

Pages: 562 - 566

Share this Article

How to Cite this Article?

A. Salai Kishwar Jahan, A. Indhumathi, "Area and Delay Minimization of Radix-2k Feedforward FFT Architecture", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20131854, Volume 3 Issue 5, May 2014, 562 - 566

80 PDF Views | 70 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Fast Fourier Transform'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1723 - 1726

Low Power Spectral Analysis for Built in Self Test by Using System on Chip

L. Maheswari, B. V. P. Prasad

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 1116 - 1120

QR Code Based Data Transmission in Mobile Devices Using AES Encryption

Ajini Asok, Arun G.

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2316 - 2319

Signal Processing Algorithm for Vital Sign Extraction of Trapped Victims

Utkarsh S. Verulkar, Dr. Abhay N. Gaikwad

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2689 - 2691

VLSI Implementation of 2048 Point FFT

Zena Vatsa, Sumaya

Share this Article

Research Paper, Electronics & Communication Engineering, China, Volume 3 Issue 10, October 2014

Pages: 1300 - 1302

Determination of Good and Bad Signal in a Given Random Signals Using MATLAB

Charles Okanda Nyatega, Ogunlade Michael Adegoke

Share this Article

Similar Articles with Keyword 'Pipelined Architecture'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2202 - 2204

FPGA Implementation of Motion Feature Extraction Employing Pipelined Architecture

M. Nivethitha, B. Venkataramanaiah

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 562 - 566

Area and Delay Minimization of Radix-2k Feedforward FFT Architecture

A. Salai Kishwar Jahan, A. Indhumathi

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1815 - 1819

Implementation of AES Algorithm in a Microblaze Processor Using System C

Rudo Duri, T. Madhavi Kumari

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 4, April 2017

Pages: 952 - 956

FIR Filter Design Based on CSD and MSD Concepts for Fixed Applications

Raseena.K.A, Vincy Mathew

Share this Article
Top