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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 5, May 2014
A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18?m CMOS Technology
Bharti D.Chaudhari, Priyesh P. Gandhi
This paper authors have design of an 8-Bit Pipelined Analog-to-Digital Converter (ADC) which is realizing using 0.18m CMOS technology. The simulation result is carried out in 0.18m technology. The Supply voltage for this Pipelined ADC is 1.8V for 0.18m Technology. The Characterization of Pipelined ADC is done in terms of SNR; SFDR; FOM; power dissipation in 0.18m CMOS technology. The Simulation Result Shows that the Sampling Rate is 200MS/s with power Dissipation of 20.2mW was achieved in 0.18m technology. The measured SNR is 50.2dB; SFDR is 67.56dB and FOM is 35.16 uJ/conv-step in 0.18m Technology.
Keywords: ADC, Dynamic charge sharing Comparator, Folded Cascade OP-AMP
Edition: Volume 3 Issue 5, May 2014
Pages: 671 - 674
How to Cite this Article?
Bharti D.Chaudhari, Priyesh P. Gandhi, "A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18?m CMOS Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20131781, Volume 3 Issue 5, May 2014, 671 - 674
138 PDF Views | 105 PDF Downloads
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