Downloads: 106 | Views: 117
Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 5, May 2014
A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18?m CMOS Technology
Bharti D.Chaudhari | Priyesh P. Gandhi
Abstract: This paper authors have design of an 8-Bit Pipelined Analog-to-Digital Converter (ADC) which is realizing using 0.18m CMOS technology. The simulation result is carried out in 0.18m technology. The Supply voltage for this Pipelined ADC is 1.8V for 0.18m Technology. The Characterization of Pipelined ADC is done in terms of SNR; SFDR; FOM; power dissipation in 0.18m CMOS technology. The Simulation Result Shows that the Sampling Rate is 200MS/s with power Dissipation of 20.2mW was achieved in 0.18m technology. The measured SNR is 50.2dB; SFDR is 67.56dB and FOM is 35.16 uJ/conv-step in 0.18m Technology.
Keywords: ADC, Dynamic charge sharing Comparator, Folded Cascade OP-AMP
Edition: Volume 3 Issue 5, May 2014,
Pages: 671 - 674
Similar Articles with Keyword 'ADC'
Downloads: 2 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Review Papers, Electronics & Communication Engineering, India, Volume 11 Issue 4, April 2022Pages: 516 - 519
Review for Design Considerations of SAR ADC in CMOS 32 NM Technology
Monu Thool | Dr. Girish D. Korde | Prof. Anant W. Hinganikar
Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015Pages: 1672 - 1675
The Design of Multi Bit Quantizer Sigma-Delta Modulator Analog to Digital Converter