International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Open Access | Double Blind Reviewed

ISSN: 2319-7064


Downloads: 122

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 3, March 2014


Design and Implementation of Convolutional Encoder and Parallel Processing Viterbi Decoder Using Verilog

Vinay.B.K | Sunil.M.P


Abstract: Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. Viterbi decoding is the best technique for decoding the convolutional codes. Convolution encoder and Viterbi decoder are widely used in many communication systems due to the excellent error control performance. This work deals with the design and implementation of convolution encoder and Viterbi decoder using Field Programmable Gate Array. By analysis the algorithm of Viterbi decoder, the project explores a practical method to design a parallel processing Viterbi decoder. It means trace back and decoder can simultaneously work in order to improve the processing speed. Due to parallelism, Total latency in decoding first bit will be 3L as compared to conventional approach which is 4L, where L is Traceback length. The experimental results show that this method is feasible.


Keywords: Viterbi, Traceback, Branch metric unit, Add compare select


Edition: Volume 3 Issue 3, March 2014,


Pages: 735 - 739


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How to Cite this Article?

Vinay.B.K, Sunil.M.P, "Design and Implementation of Convolutional Encoder and Parallel Processing Viterbi Decoder Using Verilog", International Journal of Science and Research (IJSR), Volume 3 Issue 3, March 2014, pp. 735-739, https://www.ijsr.net/get_abstract.php?paper_id=20131304

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