Design and Simulation of Four Stage Pipelining Architecture Using the Verilog
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 3, March 2014

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

The computer or any devices use the concept of parallelism for speedup of system operations. The one of parallelism technique is pipelining concept. Many devices using the pipelining for increase speed and throughput. The overall pipeline stage can be subdivided into stages such as fetch, decode, execute, store. In this paper the design and simulation of four stage pipeline can be done separately using the Xilinx ISE and Modelsim simulator. It shows how the each stage of pipeline performs the operations.

Keywords: instruction, pipeline, speed of operation, processor cycle

Edition: Volume 3 Issue 3, March 2014

Pages: 108 - 112

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How to Cite this Article?

Rakesh M. R, "Design and Simulation of Four Stage Pipelining Architecture Using the Verilog", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20131078, Volume 3 Issue 3, March 2014, 108 - 112

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