Ultra Low Power Design of Combinational Logic Circuits
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 9, September 2016

Ultra Low Power Design of Combinational Logic Circuits

M. Shyam Sundar

The dynamic power utilization of CMOS circuits is constantly turning into a noteworthy worry in Very Large Scale Integration design. This issue can be fathomed with the assistance of adiabatic method that diminishes the dynamic power utilization in the pull up network and the energy stored on the load capacitance can be recycled. A multiplexer is the essential part of the any digital circuit and a standout amongst the most used circuits. An assortment of uses a multiplexer has, where a multiplexer can be actualized for e.g. in Full Adder, Arithmetic Logic Unit (ALU), Digital Compressor and so on. This paper displays the semi adiabatic Modified Positive Feedback Adiabatic Logic (MPFAL) for low power operation through energy recovery procedure. The circuit of positive Feedback adiabatic (PFAL) inverter has been modified. Correlation with static CMOS and PFAL circuits are made to demonstrate the designs. In post-layout simulation, energy saving funds of 27 % is accomplished against the Modified PFAL Inverter, NAND, NOR gates and multiplexer circuits. The different change results are analyzed in mentor graphics.

Keywords: Adiabatic logic, PFAL, MPFAL, MUX, Universal gates

Edition: Volume 5 Issue 9, September 2016

Pages: 1554 - 1558

Share this Article

How to Cite this Article?

M. Shyam Sundar, "Ultra Low Power Design of Combinational Logic Circuits", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=17091603, Volume 5 Issue 9, September 2016, 1554 - 1558

123 PDF Views | 91 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Adiabatic logic'

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2433 - 2438

A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic

Shaswat Singh Bhardwaj, Vishal Moyal

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 2363 - 2367

Design and Analysis of f2g Gate using Adiabatic Technique

Renganayaki.G, Thiyagu.P

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1409 - 1413

Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic

C. S. Harmya Sreeja, N. Sri Krishna Yadav

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 1, January 2017

Pages: 2320 - 2323

Implementation of Low Power Adiabatic based Inverter for Dynamic Comparator

Heena Parveen, Vishal Moyal

Share this Article

Similar Articles with Keyword 'PFAL'

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 2363 - 2367

Design and Analysis of f2g Gate using Adiabatic Technique

Renganayaki.G, Thiyagu.P

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 43 - 45

Low Power Circuit Design Using Positive Feedback Adiabatic Logic

Arjun Mishra, Neha Singh

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 9, September 2016

Pages: 1554 - 1558

Ultra Low Power Design of Combinational Logic Circuits

M. Shyam Sundar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 6, June 2016

Pages: 1270 - 1274

Design and Analysis of Full Adder Using Adiabatic Logic

Durgesh Patel, Dr. S. R. P. Sinha

Share this Article

Similar Articles with Keyword 'MUX'

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 7, July 2017

Pages: 1872 - 1877

Scan Insertion on Multi Clock Design in Modern SOC?s

K. Ramini, B. Bhavani

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 7, July 2016

Pages: 2170 - 2173

Design of High Speed Flash Analog to Digital Converter Using Multiplexer and Comparator

Rana Vikram Pratap Singh Yadav, Neelam Srivastava

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1475 - 1478

New Design for Obtain Fault Tolerant Logic Gate Using Quantum-Dot Cellular Automata

Punam Prabhakar Bhalerao, Sameena Zafar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2933 - 2937

Design and Analysis of Low Power High Speed Area Efficient Multipliers using Compressors on FPGA

Ch. Naga Srinivasa Rao, K. V. B. Chandra Sekhar Rao

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 7, July 2016

Pages: 1694 - 1697

Design and Performance Analysis of TFA Cell Using CNTFET

Gaurav Agarwal, Amit Kumar

Share this Article

Similar Articles with Keyword 'Universal gates'

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 9, September 2016

Pages: 1554 - 1558

Ultra Low Power Design of Combinational Logic Circuits

M. Shyam Sundar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 9, September 2017

Pages: 951 - 953

Implementation of Artificial Neural Network for Pattern Detection in VHDL

Apurva Shukla, Prashant Puri Goswami

Share this Article
Top