Background Subtraction Algorithm for Moving Object Detection Using Denoising Architecture in FPGA
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 8, August 2013

Background Subtraction Algorithm for Moving Object Detection Using Denoising Architecture in FPGA

Anu Susan Philip

Currently, in both market and the academic communities have required applications based on image and video processing with several real-time constraints. On the other hand, detection of moving objects is a very important task in mobile robotics and surveillance applications. In order to achieve this, we are using a alternative means for real time motion detection systems. This paper proposes hardware architecture for motion detection based on the background subtraction algorithm, which is implemented on FPGAs (Field Programmable Gate Arrays). For achieving this, the following steps are executed: (a) a background image (in gray-level format) is stored in an external SRAM memory, (b) a low-pass filter is applied to both the stored and current images, (c) a subtraction operation between both images is obtained, and (d) a morphological filter is applied over the resulting image. Afterward, the gravity center of the object is calculated and sent to a PC (via RS-232 interface).

Keywords: Background subtraction, DTBDM, Similarity module, FPGA, RS-232 interface

Edition: Volume 2 Issue 8, August 2013

Pages: 151 - 157

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How to Cite this Article?

Anu Susan Philip, "Background Subtraction Algorithm for Moving Object Detection Using Denoising Architecture in FPGA ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=1201395, Volume 2 Issue 8, August 2013, 151 - 157

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