Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Review Papers | Electronics & Communication Engineering | India | Volume 5 Issue 5, May 2016

Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder

Gaurav Agarwal, Amit Kumar

The shrinkage in size of VLSI chips as well as improved energy efficiency is the need of the modern digital era. Using ternary logic instead of conventional binary logic helps to reduce circuit complexity and hence reduces chip area. Carbon nanotubes FET (CNTFET) are preferred over CMOS for logic design due to its high performance i.e. excellent transport property, low resistivity and higher current on-off ratio. The performance of ternary based logic gates is evaluated in terms of parameter such as power dissipation and delay.

Keywords: Carbon nanotube CNT, Single walled CNT SWCNT, Multiple valued logic MVL, Carbon nanotube FET CNTFET

Edition: Volume 5 Issue 5, May 2016

Pages: 787 - 791

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How to Cite this Article?

Gaurav Agarwal, Amit Kumar, "Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=10051601, Volume 5 Issue 5, May 2016, 787 - 791

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Downloads: 141 | Weekly Hits: ⮙5 | Monthly Hits: ⮙12

Review Papers, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 787 - 791

Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder

Gaurav Agarwal, Amit Kumar

Share this Article



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