Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 8, August 2013
Low Power Area Efficient Parallel Counter Architecture
Counters are specialized registers and is considered as essential building blocks for a variety of circuit operations such as programmable frequency dividers, shifters, code generators, memory select management, and various arithmetic operations. Since many applications are comprised of these fundamental operations, much research focuses on efficient counter architecture design. This paper proposes an 8-bit high speed parallel counter architecture. The counter consists of two main sections- the counting section and the state Anticipation Module.The total equivalent gate count for our proposed counter is 164 whereas the existing counter architecture consumes 266.The delay of the proposed counter architecture is 3.968ns and that of existing counter is 4.952ns. The Power consumption is 28.80mW for our proposed counter and 29.24mW for the existing one.
Keywords: parallel counter design, high speed, state anticipation module
Edition: Volume 2 Issue 8, August 2013
Pages: 90 - 94
How to Cite this Article?
Lekshmi Aravind, "Low Power Area Efficient Parallel Counter Architecture", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=04081302, Volume 2 Issue 8, August 2013, 90 - 94
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