Low Power Area Efficient Parallel Counter Architecture
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Downloads: 126

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 8, August 2013

Low Power Area Efficient Parallel Counter Architecture

Lekshmi Aravind

Counters are specialized registers and is considered as essential building blocks for a variety of circuit operations such as programmable frequency dividers, shifters, code generators, memory select management, and various arithmetic operations. Since many applications are comprised of these fundamental operations, much research focuses on efficient counter architecture design. This paper proposes an 8-bit high speed parallel counter architecture. The counter consists of two main sections- the counting section and the state Anticipation Module. The total equivalent gate count for our proposed counter is 164 whereas the existing counter architecture consumes 266. The delay of the proposed counter architecture is 3.968ns and that of existing counter is 4.952ns. The Power consumption is 28.80mW for our proposed counter and 29.24mW for the existing one.

Keywords: parallel counter design, high speed, state anticipation module

Edition: Volume 2 Issue 8, August 2013

Pages: 90 - 94

Share this Article

How to Cite this Article?

Lekshmi Aravind, "Low Power Area Efficient Parallel Counter Architecture", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=04081302, Volume 2 Issue 8, August 2013, 90 - 94

Enter Your Email Address




Similar Articles with Keyword 'high speed'

Downloads: 101

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 3016 - 3021

Low Noise & High Speed Domino Logic Circuit

Reetu Narayan, Kumar Saurabh

Share this Article

Downloads: 102

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2468 - 2472

VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture

Ghanshyam A. Chune, Vijay Bagdi

Share this Article

Similar Articles with Keyword 'parallel'

Downloads: 121

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article

Downloads: 102

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2468 - 2472

VHDL Implementation for Adaptive FIR filter and its Novel Application using Systolic Architecture

Ghanshyam A. Chune, Vijay Bagdi

Share this Article

Similar Articles with Keyword 'counter'

Downloads: 100

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

Efficient Implementation of Digital Receiver on FPGA

M. Sravani, B. Madhavi

Share this Article

Downloads: 109

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 2663 - 2667

Security Based Variable Holographic Data Encryption using Spatial Light Modulator

Aswathy.J.R, Sajan Ambadiyil, Helen Mascreen

Share this Article

Similar Articles with Keyword 'design'

Downloads: 182

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri, Syed Sazad

Share this Article

Downloads: 121

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article

Similar Articles with Keyword 'high'

Downloads: 127

Research Paper, Electronics & Communication Engineering, India, Volume 7 Issue 6, June 2018

Pages: 1662 - 1664

Enhancement of Gray Level Image by Fuzzy and Filter Technique

Monalisa Pandey, Pankaj Sharma

Share this Article

Downloads: 1

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 1842 - 1847

A Novel Mac Based Congestion Control System for VANET with Adaptive Routing

Mahanthgouda, Sridhara. K

Share this Article

Similar Articles with Keyword 'speed'

Downloads: 121

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article

Downloads: 1 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 7, July 2021

Pages: 1498 - 1500

Design of Efficient Braun Multiplier for Arithmetic Applications

Telagamalla Gopi

Share this Article

Similar Articles with Keyword 'state'

Downloads: 1

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 1842 - 1847

A Novel Mac Based Congestion Control System for VANET with Adaptive Routing

Mahanthgouda, Sridhara. K

Share this Article

Downloads: 93

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 508 - 513

Saliency Technique for Efficient Back Ground Subtraction

Aiswarya Muralidharan, S. Sivakumar

Share this Article

Similar Articles with Keyword 'module'

Downloads: 48

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 3, March 2021

Pages: 962 - 965

Design of Air Quality Analysis Monitoring Using LoRaMOTE Developing Module

Dr. L. Thulasimani, S. Sangeetha Mary, Vimalathithan Rathinasabapathy

Share this Article

Downloads: 53

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 3, March 2021

Pages: 143 - 150

VLSI Architecture Design and Implementation of CANNY Edge Detection Subsystem

Ragi R G, Jayaraj U Kidav, Roshith K

Share this Article



Top