Low Power, Noise-Free Divided By 4/5 Counter Using Domino Logic: A Survey
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 7, July 2013

Low Power, Noise-Free Divided By 4/5 Counter Using Domino Logic: A Survey

A. Veera Lakshmi, B. Ganesamoorthy

Reduction of propagation delay is very important for high speed applications. This paper gives an idea about the delay reduction on divided-by-4/5 counter. The delay is reduced by domino logic. Dynamic domino logic circuits are widely used in advanced digital Very Large Scale Integration (VLSI) circuits because it is uncomplicated to implement and low cost. Domino logic is a CMOS based approximation of the dynamic logic techniques. It was technologically advanced to speed up the circuit. Compare to static Complementary Metal Oxide Semiconductor (CMOS) logic, dynamic domino logic deals better performance. Domino gates naturally consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static Complementary Metal Oxide Semiconductor (CMOS) gate. In this paper, dynamic logic flip-flop such as Extended True-Single-Phase-Clock (E-TSPC) flip-flop based divided-by-N/N+1 counter is used for high speed and low power applications. And the proposed work is then compared with the static Complementary Metal Oxide Semiconductor (CMOS) logic.

Keywords: D-Flip Flop, Extended True Single Phase clock, Low power, High speed

Edition: Volume 2 Issue 7, July 2013

Pages: 83 - 87

Share this Article

How to Cite this Article?

A. Veera Lakshmi, B. Ganesamoorthy, "Low Power, Noise-Free Divided By 4/5 Counter Using Domino Logic: A Survey ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=0201395, Volume 2 Issue 7, July 2013, 83 - 87

94 PDF Views | 77 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'D-Flip Flop'

Research Paper, Electronics & Communication Engineering, India, Volume 8 Issue 11, November 2019

Pages: 964 - 967

Low Power and Area Efficient Carry Select Adder Using D-Flip Flop

S. Muminthaj, S. Kayalvizhi, K. Sangeetha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 83 - 87

Low Power, Noise-Free Divided By 4/5 Counter Using Domino Logic: A Survey

A. Veera Lakshmi, B. Ganesamoorthy

Share this Article

Similar Articles with Keyword 'Extended True Single Phase clock'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 847 - 850

Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops

Nemitha B, Pradeep Kumar B. P

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 83 - 87

Low Power, Noise-Free Divided By 4/5 Counter Using Domino Logic: A Survey

A. Veera Lakshmi, B. Ganesamoorthy

Share this Article

Similar Articles with Keyword 'Low power'

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri, Syed Sazad

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots' Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1723 - 1726

Low Power Spectral Analysis for Built in Self Test by Using System on Chip

L. Maheswari, B. V. P. Prasad

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 2158 - 2160

Analysis of Implicit Type Pulse Triggered Flip Flop

Richa Srivastav, Dinesh Chandra, Sumit Khandelwal

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this Article

Similar Articles with Keyword 'High speed'

Research Paper, Electronics & Communication Engineering, India, Volume 9 Issue 10, October 2020

Pages: 237 - 239

Li-Fi Based Patient Monitoring System

Vivek Sangani

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 779 - 782

High Speed Advanced Encryption Standard Using Pipelining

Mradul Upadhyay, Utsav Malviya

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 2257 - 2262

VLSI Implementation of an Optical OFDM Transmitter Using 180nm Technology

Arunlal.K.S, Saravanan.V

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 1918 - 1922

Surveillance and High Speed Analysis of Wireless Gigabit Network

Bhavani Sunkara, Rama Krishna Mullapudi

Share this Article
Top