Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 1, January 2014
Modeling and Simulation of Single Stage Voltage Controlled Oscillator using Adaptive Voltage level Technique
Neeta Yadav  | Nitin Saluja
Abstract: A single stage source coupled CMOS voltage controlled oscillator is presented here using Adaptive voltage level technique (AVL) with the advancement of minimizing the power dissipation and generating rapidly high frequency of oscillation. The single stage VCO circuit has a low phase noise due to minimizing the noise sources. The voltage controlled oscillator is used in phase lock loop (PLL) as a frequency synthesizer to generate local oscillation frequency. Power dissipation is one of the most important performance parameter here, The Adaptive Voltage level techniques have applied in presented work mitigate the power dissipation. The simulation and performance analysis of proposed circuit is evaluated in Cadence virtuoso tool. In this simulator we use 45nm standard CMOS process technology. Simulation provides comparative study of different power reduction techniques on the basis of static and dynamic power. AVL technique provides 3.97fw static power and 38.02pw dynamic power for the 0.7v supply voltage at room temperature.
Keywords: Voltage Control Oscillator, AVL, Power dissipation, Cadence Virtuoso
Edition: Volume 3 Issue 1, January 2014,
Pages: 350 - 354
How to Cite this Article?
Neeta Yadav, Nitin Saluja, "Modeling and Simulation of Single Stage Voltage Controlled Oscillator using Adaptive Voltage level Technique", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=02013816, Volume 3 Issue 1, January 2014, 350 - 354, #ijsrnet
How to Share this Article?
Similar Articles with Keyword 'Power dissipation'
Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power
Vema Vishnu Priya | G.Ramesh